The present invention is related in general to basic input/output systems (BIOS) for personal computers, and more particularly concerns a method and apparatus for reliably reading time elements from a real-time clock chip or component.
In firmware design, it is often critical to read the time or date with certainty, as the read time or date may control sensitive financial or physical operations. To read the time or date with such certainty, certain timing deadlines must be met. Many conventional computer and controller systems ignore these deadlines.
If not critical, it is at least useful to reuse code in order to save both read-only and random access memory space. It is also important to maintain as much conceptual separation between computer hardware and computer software as possible, such that one can be changed with only a minimal effect on the other.
In the basic input/output system (BIOS) of a personal computer (PC), there is generally a routine which will read the value from a hardware component called a real-time clock or RTC. The RTC puts out several time-related values, such as seconds, minutes, hours, date and year. It would be useful to use a single program to read multiple ones of these values instead of serially using several such programs, which takes more time and processing resources and uses more memory space.
A problem associated with using a single routine for reading multiple values from the RTC which comprise a time stamp is that, because of its dynamic nature, the clock could advance between calls to the common routine. Another problem is created by attempts to read the RTC while it is in the process of updating, which may result in the delivery of meaningless data.
Conventional PC RTCs are compatible with an original MOTOROLA RTC architecture. The conventional methodology used in reading MOTOROLA RTC-compatible RTCs is to write straight-line, monolithic code which reads or write the entire time, date, and time and date, which wastes space and increases software""s dependence on hardware. This code is optimized for speed inline, but makes no attempt to ensure that events beyond the control of the CPU do not occur in the middle, which could result in exceeding the permissible timing window for these read operations before the next update cycle begins. In conventional practice, specific code must be written for every combination of RTC time/date registers desired to be accessed, due to the timing constraints which force designers to write inline code and not to call out to preexisting routines. There is also no way of knowing whether unpredictable or undetectable events in the system fabric, such as system management interrupts (SMIs) or bus stalls, have caused the execution of the monolithic code to exceed a critical timing threshold. The code could therefore unknowingly deliver incorrect results. It would therefore be beneficial to devise a method and apparatus for reading a single RTC register at a time, while yet guaranteeing the return of a complete and accurate time/date, essentially free from errors caused by exceeding RTC read windows.
According to one aspect of the invention, a system, programmable medium and method are provided for reliably reading a plurality of different time elements from a clock. The clock, of which an RTC is an example, updates one or more of the time elements at the end of each of a plurality of time periods. Each time period has a nonupdate period during which the time elements are not being changed, and an update period during which the clock is updating the time elements. The clock generates an update in progress (UIP) signal for the duration of each update period. Each such update period has read window during which the time elements may be stably read. A processor coupled to the clock periodically reads the UIP signal and the time elements. The processor is programmed with a read time program which permits the reading of the time elements during the nonupdate period and the read window portion, but which does not permit the reading of time elements during that portion of the update period not falling within the read window portion.
According to another aspect of the invention, a system, programmed medium and method are usable in connection with a clock which updates a plurality of time elements once during each of a plurality of time periods. Each time period has an update period during which the clock is updating the time elements and a nonupdate period. The time period is also divisible into two alternative components: an unstable period during which the time elements may not be stably read, and a stable period in which they are. The clock issues an update in progress (UIP) signal when it is in the update period. Using the UIP signal, the processor ascertains the start and duration of the stable period and reads time elements only during this period.
The present invention provides a program that uses a single routine to retrieve any of a number of values from the registers of an RTC clock, with little or no possibility of error. As programmed with the routine, which preferably is a portion of a basic input output system (BIOS), a processor reads the RTC in order to discern the present time. The processor takes advantage of an initial period of the RTC update cycle during which, in fact, the output registers of the RTC clock do not change and may be stably read. During the update cycle of the RTC, the RTC clock outputs an update-in-progress (UIP) signal. The program permits the processor to read time elements from the RTC when the UIP signal is clear, and further permits the reading of time elements from the RTC during an initial read window when the UIP signal is set. The processor uses an internal clock to determine when the read window of the update period is about to expire, and a read operation will not be begun if there is a danger that the read window will be exceeded.
According to another aspect of the invention, the processor uses a single read time routine that permits the reading of any of a number of predetermined time elements from the RTC clock during a period in which the output registers of the RTC are stable, but which otherwise prohibits such reads.